1. Field of the Invention
The present invention relates generally to a method for detecting the phase difference between two timing signals and to a corresponding apparatus for carrying out the method.
2. Description of the Related Art
The phase synchronization of two signals, particularly two digital timing signals, is important for many applications. A high-precision, failure-protected timing generator means is centrally installed in synchronously operated communication means, for example. The timing signals generated in this timing generator means are distributed via transmitting means to all components of a communication network together with the transmitted digital information, e.g. speech information. With the aid of timing generator means equipped with phase control loops (Phase Locked Loop, PLL), timing signals are generated in the components, the phases thereof matching the phases of the incoming high-precision reference timing signals (i.e. the transmitted, or respectively, distributed timing signals).
European Patent Document EP-B1-0389 662 teaches a timing generator means with a phase control loop, for example. In the timing generator means the timing signals formed in a voltage-controlled timing oscillator are synchronized with the incoming reference timing signals with respect to their phase, or respectively, frequency. The phase difference between the timing signals and the reference timing signals is detected with the aid of a delay line formed by serially connected delay elements and of a delay-line register. The reference timing signals run through the serially connected delay elements, whereby a transit time information representing the number of delay elements passed by the reference timing signal is transferred into the delay-line register at times determined by the subsequent timing signal, respectively. With the aid of the transit time information the phase difference between the timing signal and the reference timing signal is calculated in an evaluating means, e.g. a microcomputer, whereby the calculation usually occurs with the aid of a program implemented in the evaluating means.
As described above, the delay line is formed by a plurality of serially connected delay elements. European Patent Document EP-A2-0274 606 teaches such a delay line, for example. The delay elements, or respectively, transit time members are thereby realized by n and p channel field effect transistors and invertors formed therefrom. The delay elements can comprise various transit times on the basis of the component tolerances, particularly the semiconductor component tolerances. Since the previously described transit time information is represented by the number of passed delay elements, in the detection of the phase difference whereby the number of the passed delay elements is multiplied by the transit time of a delay element considerable differences arise between the detected--i.e. calculated transit--time and the actual transit time of the reference timing signal through the delay line.
A method and an arrangement were thus proposed in German Patent Document DE-A1-195 03 035, whereby the precision of the phase difference determination can be improved, since the actual delay time--i.e. the absolute transit time--of a delay element of the delay line is exactly determined prior to the determination of the phase difference.
The method taught by German Patent Document DE-A1-195 03 035 is further detailed below using the arrangement depicted in FIG. 4.
As shown in FIG. 4, a timing signal a and a reference timing signal b are fed to the arrangement via two input terminals. The reference timing signal b--represented by a positive timing pulse edge--reaches the input D of a first flip-flop 5 (D flip-flop) and is simultaneously fed to an input terminal of a AND logic element 7. The timing signal a is applied at the timing input of the first flip-flop 5 so that, for example, the edge alternation of the reference timing signal b with the subsequent positive edge of the timing signal a reaches the input D of a subsequent second flip-flop 6 (D flip-flop) via the output Q of the first flip-flop 5. The inverted output Q' of the first flip-flop 5 comprises a high potential up to the arrival of the positive timing pulse edge of the timing signal a, for example, so that with the incoming positive timing pulse edge of the reference timing signal b both inputs of the AND logic element 7 lie at a high potential, and thus the output of the AND logic element 7 assumes a high potential. In this way the positive timing pulse edge of the reference timing signal b is fed to a delay line 1 (FIG. 4) with the aid of the output signal b' of the AND logic element 7, this line consisting of a plurality of serially connected delay elements 8. The positive timing pulse edge of the reference timing signal b, or respectively, b' thus passes through the individual delay elements 8 of the delay line 1 in succession. The individual outputs OUT of the delay elements 8 of the delay line thereby constantly change their potential such that digital status information, or respectively, transit time information--which respectively represent the number of the delay elements 8 of the delay line 1 passed by the reference timing signal b or respectively, b'--can be tapped at the outputs OUT of the delay elements 8 of the delay line 1 (e.g. by means of a decimal/binary converter DEC/BIN CONVERTER).
Given the arrival of the subsequent--e.g. positive--timing pulse edge of the timing signal a, the status of the timing signal b is connected through from the input D of the first flip-flop 5 to its output Q. The inverted output Q' of the first flip-flop 5 consequently changes from an initially high potential to a low potential. This alternation of edges, or respectively, potentials is fed to a register 2--referenced register A (FIG. 4)--which consequently takes over and stores the released transit time information of the delay line 1. The coded transit time information taken over by the register 2 thus represent the number m.sub.1 of delay elements 8 of the delay line 1 which are passed by the reference timing signal b, or respectively, b' during a differential time-span between the signal alternation of the reference timing signal b and the signal alternation of the subsequent timing signal a.
With the next--e.g. positive--timing pulse edge of the timing signal a, which is applied to the timing input of the second flip-flop 6, the edge alternation of the previously detailed reference timing signal b is connected through to the output Q of the second flip-flop 6. Another register 3--referenced register B--is actuated by these edge, or respectively, potential alternations of the output Q of the second flip-flop 6, this register thus taking over and storing further transit time information of the delay line 1. The coded transit time information now stored in the register 3 represent the number m.sub.2 of the delay elements 8 passed by the edge alternation of the reference timing signal b, or respectively, b' during one period of the timing signal a.
Since the timing pulse period of the timing signal a is known, a microprocessor 4 that serves as an evaluating means can determine the actual delay time, or respectively, transit time of the delay elements 8 of the delay line 1 depending on the number m.sub.2 of the delay elements 8 of the delay line 1 passed through during a timing pulse period of the timing signal a--which is stored in the register B--and on the known timing pulse period of the timing signal a by dividing the timing pulse period of the timing signal a by the number m.sub.2. The microprocessor 4 can subsequently determine the actual differential time-span, or respectively, delay time between the two signals by multiplying the obtained actual delay time of each delay element 8 of the delay line 1 by m.sub.1, the number of delay elements 8 of the delay line 1 that were passed during the differential time-span between the positive timing pulse edges of the reference timing signal b and of the timing signal a, for example--this number being filed in the register 2--and can calculate the phase difference within the timing signal a with the aid of the actual differential time-span, or respectively, the delay time with reference to the duration of the known pulse period of the timing signal a.
The arrangement depicted in FIG. 4 and the corresponding method for determining the phase difference between the timing signals a and b have the disadvantage, however, that a plurality of gates are necessary for determining the phase difference, particularly in the delay line 1, and the arrangement, or respectively, the method is dependent on technology.